HD643303x Hitachi, HD643303x Datasheet - Page 218

• Manufacturer Part Number: HD643303x
• Description: Hitachi Microcomputer
• Manufacturer: Hitachi

8.2.13 Timer Interrupt Enable Register (TIER)
TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel
0
1
2
3
4
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Bit
Initial value
Read/Write
Abbreviation
TIER0
TIER1
TIER2
TIER3
TIER4
—
—
7
1
Function
Enables or disables interrupt requests.
—
—
6
1
Reserved bits
—
—
5
1
203
—
—
4
1
Overflow interrupt enable
Enables or disables OVF
interrupts
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
—
—
3
1
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
OVIE
R/W
2
0
IMIEB
R/W
1
0
IMIEA
R/W
0
0