HD643303x Hitachi, HD643303x Datasheet - Page 316

• Manufacturer Part Number: HD643303x
• Description: Hitachi Microcomputer
• Manufacturer: Hitachi

Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock
sources, obtained by prescaling the system clock (ø), for input to TCNT.
Bit 2
CKS2
0
1
10.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable
generated by watchdog timer overflow, and controls external output of the reset signal.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Notes: 1. RSTCSR is write-protected by a password. For details see section 10.2.4, Notes on
Bit
Initial value
Read/Write
2. Only 0 can be written in bit 7, to clear the flag.
0
0
Bit 1
CKS1
1
1
Register Access.
Watchdog timer reset
Indicates that a reset signal has been generated
R/(W)
WRST
Bit 0
CKS0
0
1
0
1
0
1
0
1
7
0
*
2
Reset output enable
Enables or disables external output of the reset signal
RSTOE
R/W
Description
ø/2
ø/32
ø/64
ø/128
ø/256
ø/512
ø/2048
ø/4096
6
0
—
—
5
1
*1
register that indicates when a reset signal has been
301
—
—
4
1
Reserved bits
—
—
3
1
—
—
2
1
—
—
1
1
(Initial value)
—
—
0
1