MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1122

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DUART
18.3.1.9
The ULSRs, shown in
the status bits from the proper character received through the UART bus, software should read the ULSR
and then the URBR.
Table 18-16
18-14
Bits
0
1
2
3
4
5
Name
TEMT Transmitter empty
THRE Transmitter holding register empty
RFE
FE
PE
Offset: 0x0_4505, 0x0_4605
BI
Reset
describes the ULSR fields.
Line Status Registers (ULSR1 and ULSR2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
W
R
Receiver FIFO error.
0 Cleared when there are no errors in the receiver FIFO or on a read of the ULSR with no remaining receiver
1 Set when one of the characters in the receiver FIFO encounters an error (framing, parity, or break
0 Either or both the UTHR or the internal transmitter shift register has a data character. In FIFO mode, a data
1 Both the UTHR and the internal transmitter shift register are empty. In FIFO mode, both the transmitter
0 UTHR is not empty.
1 A data character has transferred from the UTHR into the internal transmitter shift register. In FIFO mode,
Break interrupt
0 Cleared when the ULSR is read or when a valid data transfer is detected (that is, STOP bit is received).
1 Received data of logic 0 for more than START bit + Data bits + Parity bit + one STOP bits length of time.
Framing error
0 Cleared when ULSR is read or when a new character is loaded into the URBR from the receiver shift
1 Invalid STOP bit for receive data (only the first STOP bit is checked). In FIFO mode, FE is set when the
Parity error
0 Cleared when ULSR is read or when a new character is loaded into URBR.
1 Unexpected parity value encountered when receiving data. In FIFO mode, the character with the error is
FIFO errors.
interrupt).
character is in the transmitter FIFO or the internal transmitter shift register.
FIFO and the internal transmitter shift register are empty.
the transmitter FIFO contains no data character.
A new character is not loaded until SIN returns to the mark state (logic 1) and a valid START is detected.
In FIFO mode, a zero character is encountered in the FIFO (the zero character is at the top of the FIFO).
In FIFO mode, only one zero character is stored.
register.
character that detected a framing error is encountered in the FIFO (that is the character at the top of the
FIFO). An attempt to resynchronize occurs after a framing error. The UART assumes that the framing error
(due to a logic 0 being read when a logic 1 (STOP) was expected) was due to a STOP bit overlapping with
the next START bit, so it assumes this logic 0 sample is a true START bit and then will receive the following
new data.
at the top of the FIFO.
RFE
0
0
Figure
Figure 18-11. Line Status Register (ULSR1 and ULSR2)
TEMT
18-11, monitor the status of the data transfer on the UART buses. To isolate
1
1
Table 18-16. ULSR Field Descriptions
THRE
1
2
BI
3
0
Description
FE
0
4
PE
0
5
Access: User read-only
OE
0
6
Freescale Semiconductor
DR
0
7