MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 282

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
5.8.3.2
As described in
down certain functional blocks within the device when they are not needed in a particular system. SCCR
can be written by the PowerPC core or by an external master. Powering down a block in this way turns off
all clocks to that block. It does not remove power. It is required that the SCCR is written to shut down a
certain functional block only when that block is idle.
5.8.3.3
PowerPC software can place the core in doze, nap, or sleep power-down states by writing to HID0 in the
core, as described in detail in the section “Hardware Implementation Register 0 (HID0),” of the e300
PowerPC Core Reference Manual. In addition, if PMCCR[SLPEN] is set when the PowerPC core request
to enter nap or sleep modes, it will also cause the system internal logic units to enter low power mode.
5.8.3.4
The device has additional low power features that allow power to be removed to a portion of the die,
allowing significant additional power savings. This mode is referred to as D3Warm (described below).
Figure 5-56
will be described in the following sections.
5-74
illustrates the power segmentation provided on the device. Sequencing in and out of D3Warm
Shutting Down Unused Blocks
Software-Controlled Power-Down States
Software-Controlled Power Supply Switching
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Functional blocks disabled using SCCR cannot respond to configuration
accesses. Any access to configuration, control, and status registers of a
disabled block is a programming error.
Section 4.5.2.3, “System Clock Control Register (SCCR),”
NOTE
SCCR provides a way to shut
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