MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 705

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The fetch FIFO can hold up to 24 descriptor pointers at a time. When the end of the current descriptor is
reached, the descriptor pointed to by the next location in the fetch FIFO will be read to launch the next
descriptor.
The Fetch Address is written into the FIFO only if the write includes the least significant byte (bits 56–63).
If Extended Address mode is used, the Extended Fetch Address must be written before or concurrent with
the Fetch Address.
Specifying a FETCH_ADRS of 0 causes the channel to generate an error and stop.
Table 14-38
14.5.1.5
The descriptor buffer (DB) consists of 8 dword registers (DB0–DB7), and contains the current descriptor
being processed by the channel. These registers are read-only, since the descriptor is always fetched from
system memory.
For more information about the fields in a descriptor, see
Freescale Semiconductor
32–63
0–31
Bits
Address
Reset
Field
Addr
R/W
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
FETCH ADRS
Names
describes the fetch FIFO fields.
Descriptor Buffer (DB)
0
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
Length0
Length1
Length2
Length3
Length4
Length5
Length6
15
Reserved, set to zero
Fetch address. Pointer to system memory location of a descriptor the host wants the SEC to fetch.
J1
J2
J3
J4
J5
J6
J7
16
Table 14-38. Fetch FIFO Field Descriptions
—
Figure 14-39. Fetch FIFO Register (FF)
17
Figure 14-40. Descriptor Buffer (DB)
Extent0
Extent1
Extent2
Extent3
Extent4
Extent5
Extent6
Header
23 24
Channel_1 0x3_1180–0x3_11BF
Channel_1 0x3_01148
—
—
—
—
—
—
—
0x0000_0000
27 28
31
W
Section 14.3.1, “Descriptor Structure.”
32
Description
31 32
FETCH_ADRS
Reserved
Pointer0
Pointer1
Pointer2
Pointer3
Pointer4
Pointer5
Pointer6
Security Engine (SEC) 2.2
63
14-63
63