MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 938

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.3.1.4
HCCPARAMS identifies multiple mode control (time-base bit functionality) addressing capability.
Figure 16-5
Table 16-7
16.3.1.5
This register is not defined in the EHCI specification. DCIVERSION is a two-byte register containing a
BCD encoding of the device controller interface. The most-significant byte of the register represents a
major revision and the least-significant byte is the minor revision.
register.
16-10
Offset 0x2_3108
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31–16
15–8
Bits
7–4
3
2
1
0
W
R
31
Name
EECP
ASP
ADC
PFL
IST
—
—
provides bit descriptions for the HCCPARAMS register.
shows the HCCPARAMS register.
Host Controller Capability Parameters (HCCPARAMS)
Device Controller Interface Version (DCIVERSION)—Non-EHCI
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared.
EHCI extended capabilities pointer. Indicates the existence of a capabilities list. A value of 0x00 indicates
no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI
configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if
implemented to maintain the consistency of the PCI header defined for this class of device.
This field is always 0.
Isochronous scheduling threshold. Indicates, relative to the current position of the executing host controller,
where software can reliably update the isochronous schedule. When bit 7 is zero, the value of the least
significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data
structures (one or more) before flushing the state. When bit 7 is a one, then host software assumes the host
controller may cache an isochronous data structure for an entire frame.
This field is always 0.
Reserved, should be cleared.
Asynchronous schedule park capability. Indicates whether the USB DR module supports the park feature
for high-speed queue heads in the asynchronous schedule. The feature can be disabled or enabled and set
to a specific level by using the asynchronous schedule park mode enable and asynchronous schedule park
mode count fields in the USBCMD register.
This field is always 1 (park feature supported).
Programmable frame list flag. Indicates whether system software can specify and use a frame list length
less that 1024 elements. Frame list size is configured via the USBCMD register frame list size field. The
frame list must always be aligned on a 4K page boundary. This requirement ensures that the frame list is
always physically contiguous.
This field is always 1.
64-bit addressing capability. Always 0; 64-bit addressing is not supported.
0 Data structures use 32-bit address memory pointers
Figure 16-5. Host Control Capability Parameters (HCCPARAMS)
Table 16-7. HCCPARAMS Register Field Descriptions
—
16 15
Description
EECP
Figure 16-6
8
7
shows the DCIVERSION
IST
Freescale Semiconductor
0
4
—
Access: Read-only
3
0
ASP PFL ADC
1
2
1
1
0
0