MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 847

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.4.3.5
Figure 15-121
Table 15-131
Freescale Semiconductor
11–15
0–12
Bits
Bits
7–8
10
13
14
15
9
Offset 0x06
Reset
W
R
Duplex
Duplex
Pause
Name
Name
Page
Able
Rx’d
Half
Full
NP
—
—
—
0
describes the fields of the ANEX register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
describes the definition for the ANEX register.
AN Expansion Register (ANEX)
Reserved, should be cleared.
Next page able. This bit is read-only and returns 1 on read. While read as set, indicates local device supports
next page function.
Page received. This bit is read-only. The bit clears on a read to the register.
0 Normal operation.
1 A new page was received and stored in the applicable AN link partner ability or AN next page register. This
bit latches high in order for software to detect while polling.
Reserved, should be cleared.
Encoding of the link partner’s PAUSE capability is shown in the PAUSE encoding table below. For priority
resolution information consult. This bit is read-only
Half-duplex capability. This bit is read-only.
0 Link partner is not capable of half-duplex mode.
1 Link partner is capable of half-duplex mode.
Full-duplex capability. This bit is read-only.
0 Link partner is not capable of full-duplex mode.
1 Link partner is capable of full-duplex mode.
Reserved, should be cleared.
PAUSE bit[8]
0
0
1
1
Table 15-130. ANLPBPA Field Descriptions (continued)
Figure 15-121. AN Expansion Register Definition
ASM_DIR bit[7]
Table 15-131. ANEX Field Descriptions
0
1
0
1
—
No PAUSE
Asymmetric PAUSE toward link partner
Symmetric PAUSE
Both symmetric PAUSE and
Asymmetric PAUSE toward local device
All zeros
Description
Description
Capability
Enhanced Three-Speed Ethernet Controllers
12
NP Able
13
Access: Read only
Page Rx’d
14
15-129
—
15