MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 704

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
14.5.1.3
The crypto-channel current descriptor pointer register (CDPR), shown in
address of the descriptor which the channel is currently processing.
The bits in the CDPR perform the functions described in
14.5.1.4
The channel contains a fetch FIFO to store a queue of pointers to descriptors that the channel will process.
The fetch FIFO, displayed in
processed. In typical operation, the host CPU will create a descriptor in memory containing all relevant
mode and location information for the SEC, then ‘launch’ the SEC by writing the address of the descriptor
to the fetch FIFO.
14-62
32–63
0–31
Bits
Reset
Field
Addr
R/W
CUR_DES_PTR_ADRS Current descriptor pointer address. Pointer to system memory location of the current
Table 14-36. Crypto-Channel Pointer Status Register PAIR_PTR Field Values (continued)
Crypto-Channel Current Descriptor Pointer Register (CDPR)
Fetch FIFO (FF)
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0x08–FF
Names
Figure 14-38. Crypto-Channel Current Descriptor Pointer Register (CDPR)
Value
0x03
0x04
0x05
0x06
0x07
—
Processing pointer dword 3
Processing pointer dword 4
Processing pointer dword 5
Processing pointer dword 6
Complete (or not yet begun) processing of header dword and pointer dwords
Reserved
Figure
Reserved, set to zero.
descriptor. This field reflects the starting location in system memory of the descriptor
currently loaded into the DB. This value is updated whenever the channel requests a fetch
of a descriptor from the controller.
The value from the fetch FIFO is transferred to the current descriptor pointer register
immediately after the fetch is completed.
This address will be used as the destination for writeback of the modified header dword, if
header writeback notification is enabled.
—
Table 14-37. CDPR Field Descriptions
14-39, contains the addresses of the first byte of descriptors to be
Channel_1 0x3_1140
0x0000_0000
31
Error
R
Table
32
Description
14-37.
CUR_DES_PTR_ADRS
Figure
14-38, contains the
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