MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 41

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure
Number
5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
7-1
7-2
7-3
7-4
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
Freescale Semiconductor
Power Management Controller Event Register .................................................................... 5-67
Power Management Controller Mask Register ..................................................................... 5-69
Power Management Controller Configuration Register 1 .................................................... 5-70
Power Management Controller Configuration Register 2 .................................................... 5-71
Power Segmentation in Deep Sleep Mode............................................................................ 5-74
Power State Transitions Supported ....................................................................................... 5-83
Example VDD Control of Device as Agent Using the Optional PMC_PWR_OK Signal ... 5-89
Example VDD Control of Device as Host ............................................................................ 5-89
Arbiter Configuration Register (ACR) ................................................................................... 6-2
Arbiter Timers Register (ATR) ............................................................................................... 6-4
Arbiter Event Register (AER)................................................................................................. 6-5
Arbiter Interrupt Definition Register (AIDR) ......................................................................... 6-6
Arbiter Mask Register (AMR) ................................................................................................ 6-7
Arbiter Event Attributes Register (AEATR) ........................................................................... 6-8
Arbiter Event Address Register (AEADR) ............................................................................. 6-9
Arbiter Event Response Register (AERR)............................................................................ 6-10
Address Bus Arbitration........................................................................................................ 6-11
An Example of Priority-Based Arbitration Algorithm ......................................................... 6-12
e300c3 Core Block Diagram................................................................................................... 7-2
e300 Programming Model—Registers.................................................................................. 7-15
e300c3 Data Cache Organization.......................................................................................... 7-29
Core Interface........................................................................................................................ 7-37
Interrupt Sources Block Diagram ........................................................................................... 8-3
System Global Interrupt Configuration Register (SICFR) ..................................................... 8-7
System Global Interrupt Vector Register (SIVCR)................................................................. 8-9
System Internal Interrupt Pending Register (SIPNR_H) ...................................................... 8-11
System Internal Interrupt Pending Register (SIPNR_L)....................................................... 8-12
System Internal Interrupt Group A Priority Register (SIPRR_A) ........................................ 8-14
System Internal Interrupt Group D Priority Register (SIPRR_D) ........................................ 8-14
System Internal Interrupt Mask Register (SIMSR_H).......................................................... 8-15
System Internal Interrupt Mask Register (SIMSR_L) .......................................................... 8-16
System Internal Interrupt Control Register (SICNR) ........................................................... 8-17
System External Interrupt Pending Register (SEPNR)......................................................... 8-18
System Mixed Interrupt Group A Priority Register (SMPRR_A) ........................................ 8-18
System Mixed Interrupt Group B Priority Register (SMPRR_B) ........................................ 8-19
System External Interrupt Mask Register (SEMSR) ............................................................ 8-20
System External Interrupt Control Register (SECNR) ......................................................... 8-21
System Error Status Register (SERSR)................................................................................. 8-22
System Error Mask Register (SERMR) ................................................................................ 8-24
System Error Control Register (SERCR).............................................................................. 8-24
System Internal Interrupt Force Register (SIFCR_H) .......................................................... 8-25
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figures
Title
Number
Page
xli