MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 23

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
14.6.4.6
14.6.4.7
14.6.5
14.6.6
14.7
15.1
15.2
15.3
15.4
15.4.1
15.5
15.5.1
15.5.2
15.5.3
15.5.3.1
15.5.3.1.1
15.5.3.1.2
15.5.3.1.3
15.5.3.1.4
15.5.3.1.5
15.5.3.1.6
15.5.3.1.7
15.5.3.1.8
15.5.3.2
15.5.3.2.1
15.5.3.2.2
15.5.3.2.3
15.5.3.2.4
15.5.3.2.5
15.5.3.2.6
15.5.3.2.7
15.5.3.2.8
15.5.3.2.9
15.5.3.2.10
15.5.3.2.11
15.5.3.2.12
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Power Saving Mode..................................................................................................... 14-75
Overview........................................................................................................................ 15-1
Features .......................................................................................................................... 15-2
Modes of Operation ....................................................................................................... 15-4
External Signals Description ......................................................................................... 15-6
Memory Map/Register Definition ............................................................................... 15-11
Snooping by Caches................................................................................................. 14-74
Interrupts.................................................................................................................. 14-75
Detailed Signal Descriptions ..................................................................................... 15-8
Top-Level Module Memory Map ............................................................................ 15-11
Detailed Memory Map............................................................................................. 15-12
Memory-Mapped Register Descriptions.................................................................. 15-22
IP Block Revision Register.................................................................................. 14-73
Master Control Register (MCR) .......................................................................... 14-74
eTSEC General Control and Status Registers...................................................... 15-22
eTSEC Transmit Control and Status Registers.................................................... 15-35
Controller ID Register (TSEC_ID).................................................................. 15-22
Controller ID Register (TSEC_ID2)................................................................ 15-23
Interrupt Event Register (IEVENT) ................................................................ 15-24
Interrupt Mask Register (IMASK) .................................................................. 15-27
Error Disabled Register (EDIS)....................................................................... 15-29
Ethernet Control Register (ECNTRL) ............................................................. 15-31
Pause Time Value Register (PTV) ................................................................... 15-33
DMA Control Register (DMACTRL) ............................................................. 15-34
Transmit Control Register (TCTRL) ............................................................... 15-35
Transmit Status Register (TSTAT)................................................................... 15-37
Default VLAN Control Word Register (DFVLAN) ........................................ 15-41
Transmit Interrupt Coalescing Register (TXIC).............................................. 15-42
Transmit Queue Control Register (TQUEUE) ................................................ 15-43
TxBD Ring 0–3 Weighting Register (TR03WT)............................................. 15-43
TxBD Ring 4–7 Weighting Register (TR47WT)............................................. 15-44
Transmit Data Buffer Pointer High Register (TBDBPH)................................ 15-45
Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7) ...................... 15-45
Transmit Descriptor Base Address Registers (TBASE0–TBASE7) ............... 15-46
Transmit Timestamp Identification Register (TMR_TXTS1–2_ID)............... 15-47
Transmit Timestamp Register (TMR_TXTS1–2_H/L) ................................... 15-47
Enhanced Three-Speed Ethernet Controllers
Contents
Chapter 15
Title
Number
Page
xxiii