MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 832

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.10.3 Timer Event Mask Register (TMR_TEMASK)
Timer event mask register. The event mask register provides control over which possible interrupt events
in the TMR_TEVENT register are permitted to participate in generating hardware interrupts to the PIC.
All implemented bits in this register are R/W and cleared upon a hardware reset. Figure 15-111 describes
the definition for the TMR_TEMASK register.
Table 15-112
15-114
Offset eTSEC1:0x2_4E08
Reset
Reset
27–31
16–23
26–31
8–13
Bits
Bits
0–5
26
14
15
24
25
6
7
W
W
R
R
16
0
ALM2EN
ALM1EN
ETS2EN
ETS1EN
PP1EN
PP2EN
Name
Name
PP3
—
describes the fields of the TMR_TEMASK register fields for the timer.
—
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 15-110. TMR_TEVENT Register Field Descriptions (continued)
—
Indicates that a periodic pulse has been generated based on FIPER3 register.
0 periodic pulse not generated
1 periodic pulse generated
Reserved
Reserved
External trigger 2 timestamp sample event enable
External trigger 1 timestamp sample event enable
Reserved
Timer ALM1 event enable
Timer ALM2 event enable
Reserved
Periodic pulse event 1 enable
Periodic pulse event 2 enable
Reserved
Table 15-112. TMR_TEMASK Register Field Descriptions
—
Table 15-111. TMR_TEMASK Register Definition
5
ETS2EN ETS1EN
6
23
7
All zeros
All zeros
PP1EN PP2EN
24
8
Description
Description
25
—
26
Freescale Semiconductor
13
—
Access: Read/Write
ALM2EN ALM1EN
14
15
31