MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 411

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10–12
13–15
16–18
Table 9-11
Freescale Semiconductor
Bits
1–3
4–8
0
9
RD_TO_PRE
ADD_LAT
WR_LAT
describes the TIMING_CFG_2 fields.
Name
CPO
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
Reserved
Additive latency. The additive latency must be set to a value less than TIMING_CFG_1[ACTTORW].
(DDR2-specific)
000 0 clocks
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 Reserved
111 Reserved
MCAS-to-preamble override. Defines the number of DRAM cycles between when a read is issued
and when the corresponding DQS preamble is valid for the memory controller. For these decodings,
“READ_LAT” is equal to the CAS latency plus the additive latency.
00000 READ_LAT + 1
00001 Reserved
00010 READ_LAT
00011 READ_LAT + 1/4
00100 READ_LAT + 1/2
00101 READ_LAT + 3/4
00110 READ_LAT + 1
00111 READ_LAT + 5/4
01000 READ_LAT + 3/2
01001 READ_LAT + 7/4
01010 READ_LAT + 2
01011 READ_LAT + 9/4
Reserved
Write latency. Note that the total write latency for DDR2 is equal to WR_LAT + ADD_LAT; the write
latency for DDR1 is 1.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
Reserved
Read to precharge (t
ADD_LAT + t
to 010; for DDR1 with burst length of 8, must be set to 100.
000 Reserved
001 1 cycle
010 2 cycles
011 3 cycles
Table 9-11. TIMING_CFG_2 Field Descriptions
RTP
cycles between read and precharge. For DDR1 with burst length of 4, must be set
RTP
). For DDR2, with a non-zero ADD_LAT value, takes a minimum of
01100 READ_LAT + 5/2
01101 READ_LAT + 11/4
01110 READ_LAT + 3
01111 READ_LAT + 13/4
10000 READ_LAT + 7/2
10001 READ_LAT + 15/4
10010 READ_LAT + 4
10011 READ_LAT + 17/4
10100 READ_LAT + 9/2
10101 READ_LAT + 19/4
10110–11111 Reserved
100 4 cycles
101–111 Reserved
Description
DDR Memory Controller
9-17