MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 117

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
0x0_8030
0x0_8034
0x0C8–
0x0D8–
0x0F8–
0x000–
0x038–
0x0CC
0x0DC
0x0BC
0x0C0
0x0C4
0x0D0
0x0D4
0x0EC
0x0FC
0x10C
0x02C
0xFFF
0x0E0
0x0E4
0x0E8
0x0F0
0x0F4
0x01F
0x100
0x104
0x108
0x020
0x024
0x028
0x030
0x034
Offset
LTEATR—Transfer error attributes register
LTEAR—Transfer error address register
LTECCR—Transfer error ECC register
Reserved
LBCR—Configuration register
LCRR—Clock ratio register
Reserved
FMR—Flash mode register
FIR—Flash instruction register
FCR—Flash command register
FBAR—Flash block address register
FPAR—Flash page address register
FBCR—Flash byte count register
Reserved
FECC0—Flash ECC block 0 register
FECC1—Flash ECC block 1 register
FECC2—Flash ECC block 2 register
FECC3—Flash ECC block 3 register
Reserved
SPI mode register (SPMODE)
SPI event register (SPIE)
SPI mask register (SPIM)
SPI command register (SPCOM)
SPI transmit register (SPITD)
SPI receive register (SPIRD)
Reserved
OMISR—Outbound message interrupt status register
OMIMR—Outbound message interrupt mask register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Register
Table 2-2. Memory Map (continued)
Serial Peripheral Interface (SPI)
DMA Registers
Access
Mixed
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
—
—
—
W
W
R
R
R
R
R
0xFFFF_FFFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0004_0000
0x8000_0008
0x0000_0 n 00
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
—
—
Figure 19-11./19-15
Figure 19-7./19-12
Figure 19-8./19-13
Figure 19-9./19-14
Figure 19-4./19-9
10.3.1.12/10-29
10.3.1.13/10-30
10.3.1.14/10-30
10.3.1.15/10-31
10.3.1.16/10-33
10.3.1.17/10-34
10.3.1.18/10-35
10.3.1.19/10-36
10.3.1.20/10-37
10.3.1.21/10-37
10.3.1.22/10-39
10.3.1.23/10-39
10.3.1.23/10-39
10.3.1.23/10-39
10.3.1.23/10-39
19.4.1.5/19-14
Section/Page
12.3.1/12-3
12.3.2/12-4
—
—
—
—
—
Memory Map
2-13