MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 739

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
0x2_4E50–
0x2_4C6C RFBPTR5*—Last Free RxBD pointer for ring 5
0x2_4C7C RFBPTR7*—Last Free RxBD pointer for ring 7
0x2_4CC0
0x2_4C70 Reserved
0x2_4C74 RFBPTR6*—Last Free RxBD pointer for ring 6
0x2_4C78 Reserved
0x2_4D94
0x2_4E0C TMR_PEVENT*—Timestamp event register
0x2_4E1C TMR_CNT_L*—Timer counter low register
0x2_4E2C Reserved
0x2_4E4C TMR_ALARM2_L*—Timer alarm 2 high register
0x2_4E7C
0x2_4E00 TMR_CTRL*—Timer control register
0x2_4E04 TMR_TEVENT*—Timestamp event register
0x2_4E08 TMR_TEMASK*—Timer event mask register
0x2_4E10 TMR_PEMASK*—Timer event mask register
0x2_4E14 TMR_STAT*—Timestamp status register
0x2_4E18 TMR_CNT_H*—Timer counter high register
0x2_4E20 TMR_ADD*—Timer drift compensation addend register
0x2_4E24 TMR_ACC*—Timer accumulator register
0x2_4E28 TMR_PRSC*—Timer prescale
0x2_4E30 TMROFF_H*—Timer offset high
0x2_4E34 TMROFF_L*—Timer offset low
0x2_4E40 TMR_ALARM1_H*—Timer alarm 1 high register
0x2_4E44 TMR_ALARM1_L*—Timer alarm 1 high register
0x2_4E48 TMR_ALARM2_H*—Timer alarm 2 high register
0x2_4E80 TMR_FIPER1*—Timer fixed period interval
0x2_4E84 TMR_FIPER2*—Timer fixed period interval
0x2_4E88 TMR_FIPER*3—Timer fixed period interval
eTSEC1
Offset
–
Reserved
Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 15-4. Module Memory Map (continued)
Name
eTSEC Future Expansion Space
1
eTSEC IEEE 1588 Registers
Access
W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
Enhanced Three-Speed Ethernet Controllers
2
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0001_0001
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0002
0x0000_0000
0x0000_0000
Reset
—
—
—
—
—
15.5.3.10.10/15-118
15.5.3.10.11/15-119
15.5.3.10.11/15-119
15.5.3.10.12/15-119
15.5.3.10.13/15-120
15.5.3.10.1/15-110
15.5.3.10.2/15-112
15.5.3.10.3/15-114
15.5.3.10.4/15-115
15.5.3.10.5/15-115
15.5.3.10.6/15-116
15.5.3.10.7/15-117
15.5.3.10.7/15-117
15.5.3.10.8/15-117
15.5.3.10.9/15-118
15.5.3.9.2/15-109
15.5.3.9.2/15-109
15.5.3.9.2/15-109
Section/Page
—
—
—
—
—
15-21