MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 970

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 0x2_340C
Reset
Universal Serial Bus Interface
The two priority states of the aging counter function each have corresponding register bits which are
programmed by the CPU. Thus, when the aging counter function is at priority state zero,
PRI_CTRL[30–31] are selected and used to drive bus priority levels. When the aging counter function is
at priority state one, PRI_CTRL[28–29] are selected and used to drive the priority.
The setting of AGE_CNT_THRESH is highly dependent on both the mix of other controllers operating on
the system bus as well as the kind of traffic moving through the USB controller. A recommended approach
is first to try leaving the aging mechanism disabled and see if the USB meets performance requirements.
If USB performance does not meet application requirements, try the following settings:
This combination works for a wide variety of applications. If this combination still does not meet
application requirements, try lowering AGE_CNT_THRESH by 5. On the contrary, the setting 40 may be
too conservative for some applications. If USB performance is acceptable at 40, try raising the value in
increments of 5. Raising AGE_CNT_THRESH benefits the other controllers on the system bus by
reducing the frequency that this USB controller raises its priority to the arbiter.
16.3.2.26 Priority Control Register (PRI_CTRL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The
priority control (PRI_CTRL) register sets the priority level for each of two priority states. The priority state
is determined by the value programmed in the AGE_CNT_THRESH register and the number of csb_clk
cycles that a particular transaction takes to complete.
16-42
Offset 0x2_3408
Reset
18–31
0–17
Bits
W
R
W
•
•
•
R
0
0
Set PRI_CTRL[pri_lvl0] to 0.
Set tPRI_CTRL[pri_lvl1] to 3.
Set AGE_CNT_THRESH to 40.
Threshold
Name
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared
Aging counter threshold value.
Table 16-34. AGE_CNT_THRESH Register Field Descriptions
Figure 16-31. Age Count Threshold (AGE_CNT_THRESH)
Figure 16-32. Priority Control (PRI_CTRL)
—
—
All zeros
All zeros
Description
17 18
Threshold
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
27
pri_lvl1 pri_lvl0
28
29
30
31
31