MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 814

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.34 Transmit Late Collision Packet Counter (TLCL)
Figure 15-85
Table 15-89
15.5.3.6.35 Transmit Excessive Collision Packet Counter (TXCL)
Figure 15-86
Table 15-90
15-96
20–31
0–19
Bits
Offset
Reset
Offset
Reset
20–31
0–19
Bits
W
W
R
R
Name
TLCL
0
0
eTSEC1:0x2_4704; eTSEC2:0x2_5704
eTSEC1:0x2_4708; eTSEC2:0x2_5708
—
describes the fields of the TLCL register.
describes the fields of the TXCL register.
Name
TXCL
describes the definition for the TLCL register.
describes the definition for the TXCL register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 15-86. Transmit Excessive Collision Packet Counter Register Definition
—
Reserved
Transmit late collision packet counter. Increments for each frame transmitted which experienced a late
collision during a transmission attempt. Late collisions are defined using the collision window field of the
half-duplex [26:31] register.
Figure 15-85. Transmit Late Collision Packet Counter Register Definition
Reserved
collisions during transmission and was aborted.
Transmit excessive collision packet counter. Increments for each frame that experienced 16
Table 15-90. TXCL Field Descriptions
Table 15-89. TLCL Field Descriptions
—
—
All zeros
All zeros
Description
Description
19 20
19 20
Freescale Semiconductor
TXCL
TLCL
Access: Read/Write
Access: Read/Write
31
31