MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 964

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.3.2.19 Endpoint Flush Register (ENDPTFLUSH)—Non-EHCI
This register is not defined in the EHCI specification. This register is only used in device mode.
16.3.2.20 Endpoint Status Register (ENDPTSTATUS)—Non-EHCI
This register is not defined in the EHCI specification. This register is only used in device mode.
16-36
Offset 0x2_31B4
Offset 0x2_31B8
Reset
Reset
31–19
18–16 FETB Flush endpoint transmit buffer. Writing a one to a bit(s) in this register will cause the associated endpoint(s) to
15–3
15–3
Bits
Bits
2–0
2–0
W
W
R
R
31
31
Name
PERB Prime endpoint receive buffer. For each endpoint, a corresponding bit is used to request a buffer prepare for a
Name
FERB Flush endpoint receive buffer. Writing a one to a bit(s) will cause the associated endpoint(s) to clear any primed
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MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared.
clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will
continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
FETB[2] (bit 18 of the register) corresponds to endpoint 2.
Reserved, should be cleared.
buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until
completion. Hardware will clear this register after the endpoint flush operation is successful. FERB[2]
corresponds to endpoint 2.
Reserved, should be cleared.
receive operation in order to respond to a USB OUT transaction. Software should write a one to the
corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use
this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB[2] corresponds
to endpoint 2.
Note that these bits will be momentarily set by hardware during hardware re-priming operations when a dTD
is retired, and the dQH is updated.
Table 16-27. ENDPTPRIME Register Field Descriptions (continued)
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Table 16-28. ENDPTFLUSH Register Field Descriptions
Figure 16-26. Endpoint Status (ENDPTSTATUS)
Figure 16-25. Endpoint Flush (ENDPTFLUSH)
21
19 18
18
ETBR
FETB
16 15
16 15
All zeros
All zeros
Description
Description
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Freescale Semiconductor
Access: Read/Write
Access: Read only
3
3
2
2
ERBR
FERB
0
0