MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 635

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
transfer of the first data. The target latency timer of the PCI controller can be optionally disabled. See
Section 13.3.3.24, “PCI Function Configuration Register,”
for more information.
When the PCI controller is in host mode it does not respond to any PCI configuration transactions. When
the PCI controller is in agent mode and the CFG_LOCK lock bit is set (see
Section 13.3.3.24, “PCI
Function Configuration
Register”) the PCI controller retries all transactions to the PCI configuration space
or the internal (on-chip) memory-mapped register space. Note that all retried accesses need to be
completed. An example of a retry is shown in
Figure
13-50.
Note that because a target can determine whether or not data is transferred (when both PCI_IRDY and
PCI_TRDY are asserted), if it wants to do only one more data transfer and then stop, it may assert
PCI_TRDY and PCI_STOP at the same time.
Target-abort refers to the abnormal termination that is used when a fatal error has occurred, or when a
target will never be able to respond. Target-abort is indicated when PCI_STOP is asserted and
PCI_DEVSEL is negated. This indicates that the target requires the transaction to be terminated and does
not want the transaction tried again. Note that any transferred data may have been corrupted.
The PCI controller terminates a transaction with target-abort in the case in which it is the intended target
of a read transaction from system memory and the data from memory is corrupt. If the PCI controller is
the intended target of a transaction and an address parity error occurs, or a data parity error occurs on a
write transaction to system memory, it continues the transaction on the PCI bus but aborts internally. The
PCI controller does not target-abort in this case.
If the PCI controller is mastering a transaction that terminates with a target-abort, undefined data is
returned on a read and write data is lost. An example of a target-abort is shown in
Figure
13-50.
An initiator may retry any target disconnect accesses, except target-abort, at a later time starting with the
address of the next non-transferred data. Retry is actually a special case of disconnect where no data
transfer occurs at all and the initiator must start the entire transaction over again.
13.4.4
Other Bus Operations
The following sections provide information on additional PCI bus operations.
13.4.4.1
Fast Back-to-Back Transactions
In the two types of fast back-to-back transactions, the first type places the burden of avoiding contention
on the initiator while the second places the burden on all potential targets. The PCI controller as a target
supports both types of fast back-to-back transactions but does not support them as an initiator. The PCI
controller as a target has the fast back-to-back enable bit hardwired to one, that is, enabled.
For the first type (governed by the initiator), the initiator may only run a fast back-to-back transaction to
the same target. For the second type, when the PCI controller detects a fast-back-to-back operation and did
not drive PCI_DEVSEL in the previous cycle, it delays the assertion of PCI_DEVSEL and PCI_TRDY
for one cycle to allow the other target to get off the bus.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
13-53