MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 899

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

A representation of the PTP packet is shown in
15.6.6.4.1
The eTSEC receive filer has been enhanced with the addition of a general-purpose event bit. This event
bit can be used in conjunction with filing table rules to identify 1588 packets and indicate these packets by
setting special timer status register bits (TMR_STAT). Additionally, 1588 packets can be easily identified
by upper-layer software by using the filer to queue all PTP packets to one or more predefined virtual
queues. See
15.6.6.5
Software has the option to write the timestamp of the transmitted frame to memory in the padding
alignment bytes (PAL) located between the TxFCB and the frame data. It is required that a minimum of
two TxBDs are used. The first points to the start of the 8-byte TxFCB. The second points to the start of
frame data. In memory, the TxFCB, and at least the first 16 bytes of the TxPAL must be adjacent, i.e.,
located in continguous memory locations, as depicted in
Freescale Semiconductor
IP header
UDP data
header
header
Layer
UDP
UDP
Preamble
Section 15.6.4.2.1, “Filing Rules,”
(Offset from
Timestamp Insertion on Transmit Packets
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
the SFD)
General Purpose Filer Rule
Octet
30-33
34-35
36-37
74
10101011
SFD
Table 15-160. PTP Payload Special Fields (continued)
Destination IP Address
IANA defines 4 multicast
address for the PTP packet
Source port number
Destination port number
Control
Timestamp Point
SRC
Figure 15-141. PTP Packet Format
Field
DEST
Figure
for further information.
L/T
IP_H
15-141.
224.0.1.129
224.0.1.130
224.0.1.131
224.0.1.132
Figure
Value
319
320
0x0
0x1
0x2
0x3
0x4
UDP_H
15-142.
DIA-RQPFR[PI
SPT-RQPFR[P
DPT-RQPFR[P
RBIFX- choose
extraction byte
eTSEC filer
Enhanced Three-Speed Ethernet Controllers
an arbitrary
ID=1011]
ID=1011]
Data
D=1100]
PID
PTP_Message
AlternatePTPdomain1
AlternatePTPdomain2
AlternatePTPdomain3
DefaultPTPdomain
Management
Comments
GeneralPort
Delay_resp
Delay_req
Follow_up
EventPort
Sync
CRC
15-181