MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 973

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.4
The USB DR module can be broken down into functional sub-blocks, which are described below.
16.4.1
The system interface block contains all the control and status registers that allow a processor to interface
to the USB DR module. These registers allow the processor to control the configuration of the module,
Freescale Semiconductor
24–25
Bits
26
27
28
29
30
31
KEEP_OTG_ON
Functional Description
ULPI_INT_EN
REFSEL[1:0]
WU_INT_EN
OTG_PORT
USB_EN
System Interface
LSF_EN
Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
The REFSEL signals are used to set the frequency value for the UTMI PLL reference clock. These
bit fields are not relevant if not in UTMI mode.
00 Reserved
01 Reference clock frequency is 24 MHz. This is the default frequency.
10 Reference clock frequency is 48 MHz
11 Reserved
Enables the OTG comparators.
0 OTG comparators disabled
1 OTG comparators enabled
Keeps the OTG comparators on during low power suspend.
0 OTG comparators disabled during suspend
1 OTG comparators enabled during suspend
This bit is used to enable the UTMI line state filter. When enabled the UTMI linestate[1:0] output
of the UTMI PHY are filtered to account for any skew between the USB differential data lines
(DP/DM).
0 Line state filter disabled
1 Line state filter enabled
UTMI mode: This bit is used to enable the USB interface. It must be set before setting RS bit in
USB CMD register.
1 Enable
0 Disable
ULPI mode: In safe mode, all USB interface signals are put into input mode or driven inactive,
except for SUSPEND_STP which is driven high. Also, the input signal DIR is forced to appear high
to the controller. This prevents any start-up problems that otherwise could occur if the PHY and
the controller take significantlly different times to complete power-on reset.
1 Normal operation
0 Safe mode
This bit is used to mask/unmask the system wakeup interrupt signal
0 System wakeup interrupt disabled
1 System wakeup interrupt enabled
Note: PORTSC[PHCD] bit must be set for the system wakeup interrupt generation.
Used to enable the ULPI low power wakeup interrupt from the PHY when the PHY is in low power
mode only.
0 ULPI low power wakeup interrupt disabled
1 ULPI low power wakeup interrupt enabled
Note: PORTSC[PHCD] bit must be set
Table 16-37. CONTROL Field Descriptions (continued)
Description
Universal Serial Bus Interface
16-45