MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 594

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
13.3.1
This section describes the registers used to allow a local bus master to access the PCI configuration space,
and generate special cycle or interrupt acknowledge transactions on the PCI bus. A special case provides
13-12
Offset
0x7C–
0x0C
0x3C
0x5C
0x6C
0xFF
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x38
0x40
0x44
0x48
0x50
0x54
0x58
0x60
0x68
0x70
0x78
PCI Configuration Access Registers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PCI error status register (PCI_ESR)
PCI error capture disable register (PCI_ECDR)
PCI error enable register (PCI_EER)
PCI error attributes capture register (PCI_EATCR)
PCI error address capture register (PCI_EACR)
PCI error extended address capture register (PCI_EEACR)
PCI error data capture register (PCI_EDCR)
PCI general control register (PCI_GCR)
PCI error control register (PCI_ECR)
PCI general status register (PCI_GSR)
PCI inbound translation address register 2 (PITAR2)
Reserved
PCI inbound base address register 2 (PIBAR2)
PCI inbound extended base address register 2 (PIEBAR2)
PCI inbound window attributes register 2 (PIWAR2)
PCI inbound translation address register 1 (PITAR1)
Reserved
PCI inbound base address register 1 (PIBAR1)
PCI inbound extended base address register 1 (PIEBAR1)
PCI inbound window attributes register 1 (PIWAR1)
PCI inbound translation address register 0 (PITAR0)
Reserved
PCI inbound base address register 0 (PIBAR0)
PCI inbound window attributes register 0 (PIWAR0)
Reserved
Table 13-5. PCI Memory-Mapped Registers
Register
PCI Control and Status Registers
PCI Error Management Registers
PCI Inbound ATU Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
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—
R
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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Freescale Semiconductor
13.3.2.10/13-22
13.3.2.11/13-22
13.3.2.12/13-23
13.3.2.13/13-24
13.3.2.14/13-24
13.3.2.11/13-22
13.3.2.12/13-23
13.3.2.13/13-24
13.3.2.14/13-24
13.3.2.11/13-22
13.3.2.12/13-23
13.3.2.13/13-24
13.3.2.1/13-15
13.3.2.2/13-16
13.3.2.3/13-17
13.3.2.4/13-18
13.3.2.5/13-19
13.3.2.6/13-20
13.3.2.7/13-20
13.3.2.8/13-20
13.3.2.9/13-21
Section/Page
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