MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 529

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
22–23
26–27
Bits
24
25
28
29
REDO
Name
LOOP
EXEN
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
AMX
UTA
NA
00 Once (normal operation)
01 Twice
10 Three times
11 Four times
Loop start/end. The first RAM word in the RAM array where LOOP is 1 is recognized as the loop
start word. The next RAM word where LOOP is 1 is the loop end word. RAM words between,
and including the start and end words, are defined as part of the loop. The number of times the
UPM executes this loop is defined in the corresponding loop fields of the M x MR.
0 The current RAM word is not the loop start word or loop end word.
1 The current RAM word is the start or end of a loop.
Note: AMX must not change values in any RAM word which begins a loop
(EXS). When an internal bus monitor time-out exception is recognized and EXEN in the RAM
word is set, the UPM branches to the special exception start address (EXS) and begins
operating as the pattern defined there specifies.
The user should provide an exception pattern to negate signals controlled by the UPM in a
controlled fashion. For DRAM control, a handler should negate RAS and CAS to prevent data
corruption. If EXEN = 0, exceptions are ignored by UPM (but not by local bus) and execution
continues. After the UPM branches to the exception start address, it continues reading until the
LAST bit is set in the RAM word.
0 The UPM continues executing the remaining RAM words, ignoring any internal bus monitor
1 The current RAM word allows a branch to the exception pattern after the current cycle if an
Address multiplexing. Determines the source of LAD during an LALE phase. Any change in the
AMX field initiates a new LALE (address) phase.
00 LAD (and/or in conjunction with LA) is the non-multiplexed address. For example, column
01 Reserved
10 LAD (and/or in conjunction with LA) is driven with the multiplexed address according to
11 LAD (and/or in conjunction with LA) is driven with the contents of MAR. Used, for example,
Note: AMX must not change values in any RAM word which begins a loop.
Note: Source ID debug mode is only supported for the AMX = 00 setting.
0 The address increment function is disabled.
1 The address is incremented in the next cycle. In conjunction with the BR n [PS], the increment
UPM transfer acknowledge. Indicates assertion of transfer acknowledge in the current cycle.
0 Transfer acknowledge is not asserted in the current cycle.
1 Transfer acknowledge is asserted in the current cycle.
In case of UPM writes, program UTA and LAST in same RAM word.
In case of UPM reads, program UTA and LAST in consecutive or same RAM words.
Redo current RAM word. Defines the number of times to execute the current RAM word.
Exception enable. Allows branching to an exception pattern at the exception start address
Next burst address. Determines when the address is incremented during a burst access.
time-out.
exception condition is detected.
value of LA n is 1 or 2 for port sizes of 8 and 16 bits, respectively.
Table 10-40. RAM Word Field Descriptions (continued)
address.
M x MR[AM]. For example, row address. See
(AMX)” for more information.
to initialize a mode.
Description
Section 10.4.4.4.7, “Address Multiplexing
Enhanced Local Bus Controller
10-81