MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 665

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.4.1.5
The DEU status register (DEUSR), displayed in
DEU internal signals. The DEUSR is read-only. Writing to this location will result in address error being
reflected in the DEU interrupt status register (DEUISR).
Table 14-14
Freescale Semiconductor
40–47
48–55
56–57
59–60
0–39
Bits
58
61
62
63
Reset
Field
Addr
R/W
Name
HALT
OFL
IFL
RD
—
—
—
ID
IE
describes the DEUSR fields.
DEU Status Register (DEUSR)
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
The number of dwords currently in the output FIFO
The number of dwords currently in the input FIFO
Reserved
Halt. Indicates that the DEU has halted due to an error.
0 DEU not halted
1 DEU halted
Note: Because the error causing the DEU to stop operating may be masked before reaching the interrupt
Reserved
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register
0 DEU is not signaling error
1 DEU is signaling error
Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register
0 DEU is not signaling done
1 DEU is signaling done
Reset done. This status bit, when high, indicates that DEU has completed its reset sequence, as reflected
in the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the register,
—
status register (ISR), the DEU interrupt status register (DEUISR) is used to provide a second source
of information regarding errors preventing normal operation.
indicating the EU is ready for operation.
39
40
Figure 14-11. DEU Status Register (DEUSR)
OFL
Table 14-14. DEUSR Field Descriptions
(Section 14.6.4.3, “Interrupt Status Register
(Section 14.6.4.3, “Interrupt Status Register
47
48
IFL
Figure
DEU 0x3_2028
55
R
Description
14-11, contains 6 fields that reflect the state of
0
56
—
57
HALT
58
(ISR)”).
(ISR)”).
59
—
60
Security Engine (SEC) 2.2
61
IE
ID
62
RD
63
14-23