MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 909

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 15-164
Freescale Semiconductor
Offset Bits
0–1
typedef unsigned short uint_16; /* choose 16-bit native type */
typedef unsigned int uint_32; /* choose 32-bit native type */
typedef struct rxbd_struct {
} rxbd;
0
1
2
3
4
5
6
7
uint_16 flags;
uint_16 length;
uint_32 bufptr;
describes the fields of the RxBD.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
RO1
W
—
M
E
F
L
I
Empty, written by the eTSEC (when cleared) and by the user (when set).
0 The data buffer associated with this BD is filled with received data, or data reception is aborted due
1 The data buffer associated with this BD is empty, or reception is currently in progress.
Receive software ownership bit.
This field is reserved for use by software. This read/write bit is not modified by hardware, nor does its
value affect hardware.
Wrap, written by user.
0 The next buffer descriptor is found in the consecutive location.
1 The next buffer descriptor is found at the location defined in RBASE.
Interrupt, written by user.
0 No interrupt is generated after this buffer is serviced.
1 IEVENT[RXB] or IEVENT[RXF] are set after this buffer is serviced. This bit can cause an interrupt
Last in frame, written by the eTSEC.
0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
First in frame, written by the eTSEC.
0 The buffer is not the first in a frame.
1 The buffer is the first in a frame.
Reserved
Miss, written by the eTSEC. (This bit is valid only if the L-bit is set and eTSEC is in promiscuous mode.)
This bit is set by the eTSEC for frames that were accepted in promiscuous mode, but were flagged as
a “miss” by the internal address recognition; thus, while in promiscuous mode, the user can use the
M-bit to quickly determine whether the frame was destined to this station.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
Table 15-164. Receive Buffer Descriptor Field Descriptions
to an error condition. The status and length fields have been updated as required.
if enabled (IMASK[RXBEN] or IMASK[RXFEN]). If the user wants to be interrupted only if RXF
occurs, then the user must disable RXB (IMASK[RXBEN] is cleared) and enable RXF
(IMASK[RXFEN] is set).
Figure 15-149. Mapping of RxBDs to a C Data Structure
Description
Enhanced Three-Speed Ethernet Controllers
15-191