1893AFLF IDT, 1893AFLF Datasheet - Page 102

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

ICS1893AF, Rev D 10/26/04
Table 9-6. PHY Address and LED Pins
P1CL
P2LI
Name
Pin
ICS1893AF Data Sheet - Release
Number
Pin
3
4
Input or
Input or
Output
Output
Type
Pin
Copyright © 2004, Integrated Circuit Systems, Inc.
PHY (Address Bit) 1 / Collision LED.
For more information on this pin, see
As an input pin:
As an output pin:
PHY (Address Bit) 2 / Link Integrity LED.
For more information on this pin, see
As an input pin:
As an output pin:
Caution:
Caution:
•
•
•
•
•
•
•
This multi-function configuration pin is:
– An input pin during either a power-on reset or a hardware reset. In
– An output pin following reset. In this case, this pin provides collision
This pin establishes the address for the ICS1893AF. When the signal
on this pin is Logic:
– Low, that address bit is set to logic zero.
– High, that address is set to logic one.
When the signal on this pin is:
– De-asserted, this state indicates the ICS1893AF does not detect any
– Asserted, this state indicates the ICS1893AF detects collisions.
The ICS1893AF asserts its Collision LED for a period of approximately
70 msec when it detects a collision.
This multi-function configuration pin is:
– An input pin during either a power-on reset or a hardware reset. In
– An output pin following reset. In this case, this pin provides link status
This pins establishes the address for the ICS1893AF. When the signal
on this pin is logic:
– Low, that address bit is set to logic zero.
– High, that address bit is set to logic one.
When the signal on this pin is:
– De-asserted, this state indicates the ICS1893AF does not have a
– Asserted, this state indicates the ICS1893AF has a valid link.
this case, this pin configures the ICS1893AF PHY Address Bit 1.
status for the ICS1893AF.
collisions.
this case, this pin configures the address of the ICS1893AF PHY
Address Bit 2.
for the ICS1893AF.
link.
All rights reserved.
This pin must not float. (See the notes at
“Multi-Function (Multiplexed) Pins: PHY Address and LED
Pins”.)
This pin must not float. (See the notes at
“Multi-Function (Multiplexed) Pins: PHY Address and LED
Pins”.)
102
Chapter 9 Pin Diagram, Listings, and Descriptions
Pin Description
Section 6.5, “Status
Section 6.5, “Status
Section 9.2.2,
Section 9.2.2,
Interface”.
Interface”.
October, 2004