1893AFLF IDT, 1893AFLF Datasheet - Page 84

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

8.11 Register 16: Extended Control Register
ICS1893AF, Rev D 10/26/04
Table 8-16
to customize the operations of the device.
Note:
1. For an explanation of acronyms used in
2. During any write operation to any bit in this register, the STA must write the default value to all
Table 8-16. Extended Control Register (register 16 [0x10])
† The default is the state of this pin at reset.
16.15
16.14
16.13
16.12
16.11
16.10
16.9
16.8
16.7
16.6
16.5
16.4
16.3
16.2
16.1
16.0
Bit
Reserved bits.
ICS1893AF Data Sheet - Release
Command Override Write
enable
ICS reserved
ICS reserved
ICS reserved
ICS reserved
PHY Address Bit 4
PHY Address Bit 3
PHY Address Bit 2
PHY Address Bit 1
PHY Address Bit 0
Stream Cipher Test Mode Normal operation
ICS reserved
NRZ/NRZI encoding
Transmit invalid codes
ICS reserved
Stream Cipher disable
lists the bits for the Extended Control Register, which the ICS1893AF provides to allow an STA
Definition
Copyright © 2004, Integrated Circuit Systems, Inc.
Disabled
Read unspecified
Read unspecified
Read unspecified
Read unspecified
For a detailed explanation of this bit’s operation,
see
For a detailed explanation of this bit’s operation,
see
For a detailed explanation of this bit’s operation,
see
For a detailed explanation of this bit’s operation,
see
For a detailed explanation of this bit’s operation,
see
Read unspecified
NRZ encoding
Disabled
Read unspecified
Stream Cipher enabled Stream Cipher disabled
Section 6.5, “Status
Section 6.5, “Status
Section 6.5, “Status
Section 6.5, “Status
Section 6.5, “Status
When Bit = 0
All rights reserved.
Table
84
8-16, see
Interface”.
Interface”.
Interface”.
Interface”.
Interface”.
Enabled
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Test mode
Read unspecified
NRZI encoding
Enabled
Read unspecified
Chapter 1, “Abbreviations and
When Bit = 1
Chapter 8 Management Register Set
RW/0
RW/0
RW/0
RW/0
RW/0
RW/0
cess
Ac-
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
SF
SC
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Acronyms”.
P4RD†
P0AC†
P3TD†
P1CL†
P2LI†
October, 2004
fault
De-
0
0
0
0
0
0
–
1
0
0
0
Hex
–
–
–
8