1893AFLF IDT, 1893AFLF Datasheet - Page 31

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

6.5 Status Interface
ICS1893AF, Rev. D 10/26/04
The ICS1893AF provides five multi-function configuration pins that report the results of continual link
monitoring by providing signals that are intended for driving LEDs. (For the pin numbers, see
Table 6-3. Pins for Monitoring the Data Link
Note:
1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input
2. A software reset does not affect the state of a multi-function configuration pin. During a software reset,
3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the
4. As outputs, the asserted state of a multi-function configuration pin is the inverse of the sense sampled
5. Adding 10K
6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII
P0AC
P1CL
P2LI
P3TD
P4RD
ICS1893AF Data Sheet - Release
that is sampled when the ICS1893AF exits the reset state. After sampling is complete, these pins are
output pins that can drive status LEDs.
all multi-function configuration pins are outputs.
address of the ICS1893AF. LEDs may be placed in series with these resistors to provide a designated
status indicator as described in Table 6-3.
Caution:
during reset. This inversion provides a signal that can illuminate an LED during an asserted state. For
example, if a multi-function configuration pin is pulled down to ground through an LED and a
current-limiting resistor, then the sampled sense of the input is low. To illuminate this LED for the
asserted state, the output is driven high.
power-ramp conditions.
tri-stated.)
Pin
AC (Link Activity) LED
CL (Collisions) LED
LI (Link Integrity) LED
TD (Transmit Data) LED
RD (Receive Data) LED
LED Driven by the Pin’s Output Signal
All pins listed in Table 6-3 must not float.
resistors across the LEDs ensures the PHY address is fully defined during slow VDD
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
31
Chapter 6 Interface Overviews
Table
October, 2004
9.2.2.)