1893AFLF IDT, 1893AFLF Datasheet - Page 20

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

5.1.2 Specific Reset Operations
5.1.2.1 Hardware Reset
5.1.2.2 Power-On Reset
ICS1893AF, Rev D 10/26/04
This section discusses the following specific ways that the ICS1893AF can be reset:
•
•
•
Note:
Entering Hardware Reset
Holding the active-low RESETn pin low for a minimum of five REF_IN clock cycles initiates a hardware
reset (that is, the ICS1893AF enters the reset state). During reset, the ICS1893AF executes the steps
listed in
Exiting Hardware Reset
After the signal on the RESETn pin transitions from a low to a high state, the ICS1893AF completes in 640
ns (that is, in 16 REF_IN clocks) steps 1 through 5, listed in
five steps are completed, the Serial Management Port is ready for normal operations, but this action does
not signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and
receive clock (RXCLK) are available, which is typically 53 ms after the RESETn pin goes high. [For details
on this transition, see
Note:
1. The MAC/Repeater Interface is not available for use until the TXCLK and RXCLK are valid.
2. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit
Entering Power-On Reset
When power is applied to the ICS1893AF, it waits until the potential between VDD and VSS achieves a
minimum voltage before entering reset and executing the steps listed in
After entering reset from a power-on condition, the ICS1893AF remains in reset for approximately 20 s.
(For details on this transition, see
Exiting Power-On Reset
The ICS1893AF automatically exits reset and performs the same steps as for a hardware reset. (See
Section 5.1.1.2, “Exiting
Note:
Hardware reset (using the RESETn pin)
Power-on reset (applying power to the ICS1893AF)
Software reset (using Control Register bit 0.15)
that is used to initiate a software reset.
ICS1893AF Data Sheet - Release
At the completion of a reset (either hardware, power-on, or software), the ICS1893AF sets all
registers to their default values.
The only difference between a hardware reset and a power-on reset is that during a power-on
reset, the ICS1893AF isolates its RESETn input pin. All other functionality is the same. As with a
hardware reset, Control Register bit 0.15 does not represent the status of a power-on reset.
Section 5.1.1.1, “Entering
Section 10.5.16, “Reset: Hardware Reset and
Reset”.)
Copyright © 2004, Integrated Circuit Systems, Inc.
Section 10.5.15, “Reset: Power-On
Reset”.
All rights reserved.
20
Section 5.1.1.2, “Exiting
Power-Down”.]
Reset”.)
Chapter 5 Operating Modes Overview
Section 5.1.1.1, “Entering
Reset”. After the first
October, 2004
Reset”.