1893AFLF IDT, 1893AFLF Datasheet - Page 62

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

8.2.8 Duplex Mode (bit 0.8)
8.2.9 Collision Test (bit 0.7)
8.2.10 IEEE Reserved Bits (bits 0.6:0)
ICS1893AF, Rev D 10/26/04
This bit provides a means of controlling the ICS1893AF Duplex Mode. Its operation depends on several
other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the
ICS1893AF is configured for:
•
•
This bit controls the ICS1893AF Collision Test function. When an STA sets bit 0.7 to logic:
•
•
The IEEE reserves these bits for future use. When an STA:
•
•
The ICS1893AF uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1893AF, an STA must maintain the default value of these bits. Therefore, ICS recommends that during
any STA write operation, an STA write the default value to all reserved bits, even those bits that are Read
Only.
Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893AF isolates bit 0.8 and uses the
DPXSEL input pin to establish the Duplex mode for the ICS1893AF. In this Hardware mode:
Software mode (that is, the HW/SW pin is logic one), the function of bit 0.8 depends on the
Auto-Negotiation Enable bit, 0.12. When the auto-negotiation process is:
Zero, the ICS1893AF disables the collision detection circuitry for the Collision Test function. In this case,
the COL signal does not track the TXEN signal. (The default value for this bit is logic zero, that is,
disabled.)
One, as per the ISO/IEE 8802-3 standard, clause 22.2.4.1.9, the ICS1893AF enables the collision
detection circuitry for the Collision Test function, even if the ICS1893AF is in Loopback mode (that is, bit
0.14 is set to 1). In this case, the Collision Test function tracks the Collision Detect signal (COL) in
response to the TXEN signal. The ICS1893AF asserts the Collision signal (COL) within 512 bit times of
receiving an asserted TXEN signal, and it de-asserts COL within 4 bit times of the de-assertion of the
TXEN signal.
Reads a reserved bit, the ICS1893AF returns a logic zero.
Writes to a reserved bit, it must use the default value specified in this data sheet.
– Bit 0.8 is undefined.
– The ICS1893AF provides a Duplex Mode Status bit (in the QuickPoll Detailed Status Register, bit
– Enabled, the ICS1893AF isolates bit 0.8 and relies upon the results of the auto-negotiation process
– Disabled, bit 0.8 determines the Duplex mode. Setting bit 0.8 to logic:
ICS1893AF Data Sheet - Release
17.14), which always shows the setting of an active link.
to establish the duplex mode.
• Zero selects half-duplex operations.
• One selects full-duplex operations. (When the ICS1893AF is operating in Loopback mode, it
isolates bit 0.8, which has no effect on the operation of the ICS1893AF.)
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
62
Chapter 8 Management Register Set
October, 2004