1893AFLF IDT, 1893AFLF Datasheet - Page 90

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

8.12.5 100Base PLL Lock Error (bit 17.9)
8.12.6 False Carrier (bit 17.8)
8.12.7 Invalid Symbol (bit 17.7)
ICS1893AF, Rev D 10/26/04
The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893AF has ever
experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming
100Base data stream. If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
8.1.4.1, “Latching High Bits”
Note:
The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893AF in 100Base
mode.
A False Carrier occurs when the ICS1893AF begins evaluating potential data on the incoming 100Base
data stream, only to learn that it was not a valid /J/K/. If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
8.1.4.1, “Latching High Bits”
Note:
The Invalid Symbol bit indicates to an STA the detection of an Invalid Symbol in a 100Base data stream by
the ICS1893AF.
When the ICS1893AF is receiving a packet, it examines each received Symbol to ensure the data is error
free. If an error occurs, the port indicates this condition to the MAC/repeater by asserting the RXER signal.
In addition, the ICS1893AF sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
8.1.4.1, “Latching High Bits”
Note:
Zero, it indicates that a PLL Lock Error has not occurred since either the last read or reset of this register.
One, it indicates that a PLL Lock Error has occurred since either the last read or reset of this register.
Zero, it indicates a False Carrier has not been detected since either the last read or reset of this register.
One, it indicates a False Carrier was detected since either the last read or reset of this register.
Zero, it indicates an Invalid Symbol has not been detected since either the last read or reset of this
register.
One, it indicates an Invalid Symbol was detected since either the last read or reset of this register.
ICS1893AF Data Sheet - Release
This bit has no definition in 10Base-T mode.
This bit has no definition in 10Base-T mode.
This bit has no definition in 10Base-T mode.
Copyright © 2004, Integrated Circuit Systems, Inc.
and
and
and
Section 8.1.4.2, “Latching Low
Section 8.1.4.2, “Latching Low
Section 8.1.4.2, “Latching Low
All rights reserved.
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Chapter 8 Management Register Set
October, 2004
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