1893AFLF IDT, 1893AFLF Datasheet - Page 34

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

7.1 Functional Block: Media Independent Interface
ICS1893AF, Rev D 10/26/04
All ICS1893AF MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the
ICS1893AF MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz
(for 10Base-T operations).
The Media Independent Interface (MII) consists of two primary components:
1. An interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893AF).
2. An interface between the PHY (the ICS1893AF) and an STA (Station Management entity). The
The ICS1893AF Management Register set (discussed in
of the following:
•
•
•
Basic Management registers.
As defined in the ISO/IEC 8802-3 standard, these registers include the following:
Extended Management registers.
As defined in the ISO/IEC 8802-3 standard, the ICS1893AF supports Extended registers that provide
access to the Organizationally Unique Identifier and all auto-negotiation functionality.
ICS (Vendor-Specific) Management registers.
The ICS1893AF provides vendor-specific registers for enhanced PHY operations. Among these is the
QuickPoll Detailed Status Register that provides a comprehensive and consolidated set of real-time PHY
information. Reading the QuickPoll register enables the MAC to obtain comprehensive status data with a
single register access.
– Control Register (register 0), which handles basic device configuration
– Status Register (register 1), which reports basic device capabilities and status
This MAC-PHY part of the MII consists of three subcomponents:
a. A synchronous Transmit interface that includes the following signals:
b. A synchronous Receive interface that includes the followings signals:
c. A Media Status or Control interface that consists of a Carrier Sense signal (CRS) and a Collision
STA-PHY part of the MII is a two-wire, Serial Management Interface that consists of the following:
a. A clock (MDC)
b. A synchronous, bi-directional data signal (MDIO) that provides an STA with access to the
ICS1893AF Data Sheet - Release
Detection signal (COL).
ICS1893AF Management Register set
(1) A data nibble, TXD[3:0]
(2) An error indicator, TXER
(3) A delimiter, TXEN
(4) A clock, TXCLK
(1) A data nibble, RXD[3:0]
(2) An error indicator, RXER
(3) A delimiter, RXDV
(4) A clock, RXCLK
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
34
Chapter 8, “Management Register
Chapter 7 Functional Blocks
Set”) consists
October, 2004