1893AFLF IDT, 1893AFLF Datasheet - Page 41

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

7.3.3 PCS/PMA Transmit Modules
7.3.3.1 PCS Transmit Module
7.3.3.2 PMA Transmit Module
ICS1893AF, Rev. D 10/26/04
Both the PCS and PMA sublayers have Transmit modules.
The ICS1893AF PCS Transmit module accepts nibbles from the MAC/Repeater Interface and converts the
nibbles into 5-bit ‘code groups’ (referred to here as ‘symbols’). In addition, the PCS Transmit module
performs a parallel-to-serial conversion on the symbols, and subsequently passes the resulting serial bit
stream to the PMA sublayer.
The first 16 nibbles of each MAC/Repeater Frame represent the Frame Preamble. The PCS replaces the
first two nibbles of the Frame Preamble with the Start-of-Stream Delimiter (SSD), that is, the symbols /J/K/.
After receipt of the last Frame nibble, detected when TX_EN = FALSE, the PCS appends to the end of the
Frame an End-of-Stream Delimiter (ESD), that is, the symbols /T/R/. (The ICS1893AF PCS does not alter
any other data included within the Frame.)
The PCS Transmit module also performs collision detection. In compliance with the ISO/IEC specification,
when the transmission and reception of data occur simultaneously and the ICS1893AF is in:
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•
The ICS1893AF PMA Transmit module accepts a serial bit stream from its PCS and converts the data into
NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium
Dependent (TP-PMD) sublayer.
The ICS1893AF PMA Transmit module uses a digital PLL to synthesize a transmit clock from the Clock
Reference Interface. When the ICS1893AF is configured for an interface that is:
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•
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Note:
1. All of the TXCLK signals are derived from the REF_IN signal that goes to the digital PLL.
2. For the MII, for both the 10Base-T and 100Base-TX modes, the clock that is generated synchronizes
Half-duplex mode, the ICS1893AF asserts the collision detection signal (COL).
Full-duplex mode, COL is always FALSE.
10M MII (that is, 10Base-T), the TXCLK signal is 2.5 MHz
10M Serial Interface, the TXCLK signal is 10 MHz
Either of the following, the TXCLK signal (a buffered version of the REF_IN signal) is 25 MHz:
– 100M MII (that is, 100Base-TX)
– 100M Symbol Interface
ICS1893AF Data Sheet - Release
all data transfers across the MII.
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
41
Chapter 7 Functional Blocks
October, 2004