1893AFLF IDT, 1893AFLF Datasheet - Page 94

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

8.13.2 Polarity Reversed (bit 18.14)
8.13.3 ICS Reserved (bits 18.13:6)
8.13.4 Jabber Inhibit (bit 18.5)
8.13.5 ICS Reserved (bit 18.4)
8.13.6 Auto Polarity Inhibit (bit 18.3)
8.13.7 SQE Test Inhibit (bit 18.2)
ICS1893AF, Rev D 10/26/04
The Polarity Reversed bit is used to inform an STA whether the ICS1893AF has detected that the signals
on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity is:
•
•
Note:
See
The Jabber Inhibit bit allows an STA to disable Jabber Detection. When an STA sets this bit to:
•
•
See
The Auto Polarity Inhibit bit allows an STA to prevent the automatic correction of a polarity reversal on the
Twisted-Pair Receive pins (TP_RXP and TP_RXN). If an STA sets this bit to logic:
•
•
Note:
The SQE Test Inhibit bit allows an STA to prevent the generation of the Signal Quality Error pulse. When an
STA sets this bit to logic:
•
•
The SQE Test provides the ability to verify that the Collision Logic is active and functional. A 10Base-T SQE
test is performed by pulsing the Collision signal for a short time after each packet transmission completes,
that is, after TXEN goes inactive.
Note:
1. The SQE Test is automatically inhibited in full-duplex and repeater modes, thereby disabling the
2. This bit is a control bit and not a status bit. Therefore, it is not updated to indicate this automatic
Correct, the ICS1893AF sets bit 18.14 to a logic zero.
Reversed, the ICS1893AF sets bit 18.14 to logic one.
Zero, the ICS1893AF enables 10Base-T Jabber checking.
One, the ICS1893AF disables its check for a Jabber condition during data transmission.
Zero (the default), the ICS1893AF automatically corrects a polarity reversal on the Twisted-Pair Receive
pins.
One, the ICS1893AF either disables or inhibits the automatic correction of reversed Twisted-Pair
Receive pins.
Zero, the ICS1893AF enables its SQE Test generation.
One, the ICS1893AF disables its SQE Test generation.
functionality of this bit.
inhibiting of the SQE test in full-duplex mode or repeater mode.
Section 8.11.2, “ICS Reserved (bits
Section 8.11.2, “ICS Reserved (bits
ICS1893AF Data Sheet - Release
The ICS1893AF can detect this situation and perform all its operations normally, independent of
the reversal.
This bit is also used to correct a reversed signal polarity for 100Base-TX operations.
Copyright © 2004, Integrated Circuit Systems, Inc.
16.14:11)”, the text for which also applies here.
16.14:11)”, the text for which also applies here.
All rights reserved.
94
Chapter 8 Management Register Set
October, 2004