1893AFLF IDT, 1893AFLF Datasheet - Page 86

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

8.11.7 Invalid Error Code Test (bit 16.2)
8.11.8 ICS Reserved (bit 16.1)
8.11.9 Stream Cipher Disable (bit 16.0)
ICS1893AF, Rev D 10/26/04
The Invalid Error Code Test bit allows an STA to force the ICS1893AF to transmit symbols that are typically
classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the
serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC
4B/5B definition.
When this bit is logic:
•
•
Table 8-17. Invalid Error Code Translation Table
See
The Stream Cipher Disable bit allows an STA to control whether the ICS1893AF employs the Stream
Cipher Scrambler in the transmit and receive data paths. When this bit is set to logic:
•
•
Note:
Symbol
Zero, the ISO/IEC defined 4B/5B translation takes place.
One – and the TXER signal is asserted by the MAC/repeater – the MII input nibbles are translated
according to
Zero, the Stream Cipher Encoder and Decoder are both enabled for normal operations.
One, the Stream Cipher Encoder and Decoder are disabled. This action results in an unscrambled data
stream (for example, the ICS1893AF transmits unscrambled IDLES, and so forth.
V (S)
Section 8.11.2, “ICS Reserved (bits
ICS1893AF Data Sheet - Release
V
V
V
V
H
V
V
R
V
V
K
V
T
J
I
The Stream Cipher Scrambler can be used only for 100-MHz operations.
Invalid Code
Invalid Code
Invalid Code
Invalid Code
Error
Invalid Code
Invalid Code
ESD
Invalid Code
ESD
Invalid Code
SSD
Invalid Code
Invalid Code
SSD
Idle
Table
Meaning
8-17.
Copyright © 2004, Integrated Circuit Systems, Inc.
MII Input
Nibble
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
16.14:11)”, the text for which also applies here.
Translation
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00000
00001
00010
00100
00101
00000
10000
00011
00110
01101
01100
10001
11001
11000
00111
11111
86
Chapter 8 Management Register Set
October, 2004