1893AFLF IDT, 1893AFLF Datasheet - Page 61

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

8.2.5 Low Power Mode (bit 0.11)
8.2.6 Isolate (bit 0.10)
8.2.7 Restart Auto-Negotiation (bit 0.9)
ICS1893AF, Rev. D 10/26/04
This bit provides one way to control the ICS1893AF low-power mode function. When bit 0.11 is logic:
•
•
Note:
This bit controls the ICS1893AF Isolate function. When bit 0.10 is logic:
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•
The default value for bit 0.10 depends upon the PHY address of
•
•
This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is
logic one). When bit 0.12 is logic:
•
•
Zero, there is no impact to ICS1893AF operations.
One, the ICS1893AF enters the low-power mode. In this case, the ICS1893AF disables all internal
functions and drives all MAC/repeater output pins low except for those that support the MII Serial
Management Port. In addition, the ICS1893AF internally activates the TPTRI function to tri-state the
signals on the Twisted-Pair Transmit pins (TP_TXP and TP_TXN) and achieve additional power savings.
Zero, there is no impact to ICS1893AF operations.
One, the ICS1893AF electrically isolates its data paths from the MAC/Repeater Interface. The
ICS1893AF places all MAC/repeater output signals (TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL,
and CRS) in a high-impedance state and it isolates all MAC/repeater input signals (TXD[3:0], TXEN, and
TXER). In this mode, the Serial Management Interface continues to operate normally (that is, bit 0.10
does not affect the Management Interface).
Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893AF isolates itself from
the MAC/Repeater Interface.
Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893AF does not
isolate its MAC/Repeater Interface.
Zero, the Auto-Negotiation sublayer is disabled, and the ICS1893AF isolates any attempt by the STA to
set bit 0.9 to logic one.
One (as set by an STA), the ICS1893AF restarts the auto-negotiation process. Once the auto-negotiation
process begins, the ICS1893AF automatically sets this bit to logic zero, thereby providing the
self-clearing feature.
ICS1893AF Data Sheet - Release
There are two ways the ICS1893AF can enter low-power mode. When entering low-power mode:
•
•
By setting bit 0.11 to logic one, the ICS1893AF maintains the value of all Management Register
bits except the latching high (LH) and latching low (LL) status bits, which are re-initialized to their
default values instead. (For more information on latching high and latching low bits, see
8.1.4.1, “Latching High Bits”
During a reset, the ICS1893AF sets all management register bits to their default values.
Copyright © 2004, Integrated Circuit Systems, Inc.
and
Section 8.1.4.2, “Latching Low
All rights reserved.
61
Table
8-16. If the PHY address:
Chapter 8 Management Register Set
Bits”.)
October, 2004
Section