1893AFLF IDT, 1893AFLF Datasheet - Page 85

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

8.11.1 Command Override Write Enable (bit 16.15)
8.11.2 ICS Reserved (bits 16.14:11)
8.11.3 PHY Address (bits 16.10:6)
8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5)
8.11.5 ICS Reserved (bit 16.4)
8.11.6 NRZ/NRZI Encoding (bit 16.3)
ICS1893AF, Rev. D 10/26/04
The Command Override Write Enable bit provides an STA the ability to alter the Command Override Write
(CW) bits located throughout the MII Register set. A two-step process is required to alter the value of a CW
bit:
1. Step one is to issue a Command Override Write, (that is, set bit 16.15 to logic one). This step enables
2. Step two is to write to the register that includes the CW bit which requires modification.
Note:
ICS is reserving these bits for future use. Functionally, these bits are equivalent to IEEE Reserved bits.
When one of these reserved bits is:
•
•
ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893AF,
an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write
the default value of any reserved bits during all management register write operations.
These five bits hold the Serial Management Port Address of the ICS1893AF. During either a hardware
reset or a power-on reset, the PHY address is read from the LED interface. (For information on the LED
interface, see
Address and LED
Address bits is unaffected by a software reset.)
The Stream Cipher Scrambler Test Mode bit is used to force the ICS1893AF to lose LOCK, thereby
requiring the Stream Cipher Scrambler to resynchronize.
See
This bit allows an STA to control whether NRZ (Not Return to Zero) or NRZI (Not Return to Zero, Invert on
One) encoding is applied to the serial transmit data stream in 100Base-TX mode. When this bit is logic:
•
•
Read by an STA, the ICS1893AF returns a logic zero.
Written to by an STA, the STA must use the default value specified in this data sheet.
Zero, the ICS1893AF encodes the serial transmit data stream using NRZ encoding.
One, the ICS1893AF encodes the serial transmit data stream using NRZI encoding.
ICS1893AF Data Sheet - Release
the next MDIO write to have the ability to alter any CW bit.
Section 8.11.2, “ICS Reserved (bits
The Command Override Write Enable bit is a Self-Clearing bit that is automatically reset to logic
zero after the next MII write, thereby allowing only one subsequent write to alter the CW bits in a
single register. To alter additional CW bits, the Command Override Write Enable bit must once
again be set to logic one.
Section 6.5, “Status Interface”
Pins”). The PHY address is then latched into this register. (The value of each of the PHY
Copyright © 2004, Integrated Circuit Systems, Inc.
16.14:11)”, the text for which also applies here.
All rights reserved.
and
85
Section 9.2.2, “Multi-Function (Multiplexed) Pins: PHY
Chapter 8 Management Register Set
October, 2004