1893AFLF IDT, 1893AFLF Datasheet - Page 19

• Manufacturer Part Number: 1893AFLF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT
• Type: Integrated PHY Transceiverr

Specifications of 1893AFLF

• Rohs: yes
• Product: Ethernet Transceivers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.47 V
• Supply Voltage - Min: 3.14 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-48
• Ethernet Connection Type: 100Base-TX, 10Base-T
• Maximum Supply Current: 160 mA
• Minimum Operating Temperature: 0 C
• Standard Supported: 802.3
• Part # Aliases: ICS1893AFLF

5.1 Reset Operations
5.1.1 General Reset Operations
5.1.1.1 Entering Reset
5.1.1.2 Exiting Reset
5.1.1.3 Hot Insertion
ICS1893AF, Rev. D 10/26/04
This section first discusses reset operations in general and then specific ways in which the ICS1893AF can
be configured for various reset options.
The following reset operations apply to all the specific ways in which the ICS1893AF can be reset, which
are discussed in
When the ICS1893AF enters a reset condition (either through hardware, power-on reset, or software), it
does the following:
1. Isolates the MAC/Repeater Interface input pins
2. Drives all MAC/Repeater Interface output pins low
3. Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
4. Initializes all its internal modules and state machines to their default states
5. Enters the power-down state
6. Initializes all internal latching low (LL), latching high (LH), and latching maximum (LMX) Management
When the ICS1893AF exits a reset condition, it does the following:
1. Exits the power-down state
2. Latches the Serial Management Port Address of the ICS1893AF into the Extended Control Register,
3. Enables all its internal modules and state machines
4. Sets all Management Register bits to either (1) their default values or (2) the values specified by their
5. Enables the Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
6. Resynchronizes both its Transmit and Receive Phase-Locked Loops, which provide its transmit clock
7. Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition
As with the ICS189X products, the ICS1893AF reset design supports ‘hot insertion’ of its MII. (That is, the
ICS1893AF can connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to
the MAC/repeater.)
ICS1893AF Data Sheet - Release
Register bits to their default values
bits 16.10:6. [See
associated ICS1893AF input pins, as determined by the HW/SW pin
(TXCLK) and receive clock (RXCLK)
is removed
Section 5.1.2, “Specific Reset
Section 8.11.3, “PHY Address (bits
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
Operations”.
19
16.10:6)”.]
Chapter 5 Operating Modes Overview
October, 2004