ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 240

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.13.5
24.13.5.1
Figure 24-23. Read Access Ordered by a MASTER
24.13.5.2
32058J-AVR32-04/11
EOSVACC
SVREAD
TXRDY
SVACC
NACK
TWD
Data Transfer
Read Operation
Write Operation
S
ADR
TWI answers with a NACK
SADR does not match,
As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT rec-
ommended in SLAVE mode.
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address
starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direc-
tion of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded
in the THR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 24-23 on page 240
Notes:
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address
is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in
this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the
RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 24-24 on page 241
R
NA
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from THR to the shift register and set when
DATA
this data has been acknowledged or non acknowledged.
NA
P/S/Sr
describes the write operation.
describes the Write operation.
Write THR
SADR
TWI answers with an ACK
SADR matches,
R
SVREAD has to be taken into account only while SVACC is active
A
DATA
A
ACK/NACK from the Master
A
DATA
AT32UC3A
NA
S/Sr
Read RHR
240