ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 391

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 27-24. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip
Figure 27-25. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects.
32058J–AVR32–04/11
Read2 controlling
Write2 controlling
Read1 controlling
Read1 controlling
NBS0, NBS1,
signal(NWE)
signal(NRD)
signal(NRD)
signal(NRD)
A0, A1
NBS0, NBS1,
CLK_SMC
A[25:2]
D[15:0]
A[25:2]
A0, A1
CLK_SMC
D[15:0]
selects.
TDF_CYCLES = 6
• read access followed by a write access on the same chip select,
with no TDF optimization.
Read1 cycle
TDF_CYCLES = 4
Read1 cycle
Read1 hold = 1
Read1 hold = 1
Chip Select Wait State
TDF_CYCLES = 4
Read to Write
Wait State
TDF_CYCLES = 6
Chip Select
Wait State
2 TDF WAIT STATES
5 TDF WAIT STATES
Write2 setup = 1
(optimization disabled)
TDF_MODE=0
Write 2 cycle
AT32UC3A
(optimization disabled)
TDF_MODE=0
Read2 setup = 1
Read 2 cycle
391