ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 374

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.6.4.1
32058J–AVR32–04/11
– NRD Waveform
Read Waveforms
The read cycle is shown on
The read cycle starts with the address setting on the memory address bus, i.e.:
Figure 27-9. Standard Read Cycle
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD ris-
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD ris-
NBS0, NBS1,
falling edge;
ing edge;
ing edge.
A0, A1
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices.
A[25:2]
D[15:0]
CLK_SMC
NRD
NCS
NCS_RD_SETUP
NRD_SETUP
Figure
27-9.
NCS_RD_PULSE
NRD_PULSE
NRD_CYCLE
NRD_HOLD
AT32UC3A
NCS_RD_HOLD
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