ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 595

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.8.2.20
Offset:
Register Name:
Access Type:
Reset Value:
• CH_EN: Channel Enabled
If set, the DMA channel is currently enabled.
If cleared, the DMA channel does no longer transfer data.
• CH_ACTIVE: Channel Active
If set, the DMA channel is currently trying to source USB data.
If cleared, the DMA channel is no longer trying to source USB data.
When a USB data transfer is completed, this bit is automatically reset.
• EOT_STA: End of USB Transfer Status
Set by hardware when the completion of the usb data transfer has closed the dma transfer. It is valid only if
BUFF_CLOSE_EN=1.
This bit is automatically cleared when read by software.
• EOCH_BUFF_STA: End of Channel Buffer Status
Set by hardware when the Channel Byte Count downcounts to zero.
This bit is automatically cleared when read by software.
• DESC_LD_STA: Descriptor Loaded Status
Set by hardware when a Descriptor has been loaded from the HSB bus.
This bit is automatically cleared when read by software.
32058J–AVR32–04/11
31
23
15
0
0
–
7
–
USB Device DMA Channel X Status Register (UDDMAX_STATUS)
DESC_LD_
STA
30
22
14
ru
0
0
–
6
0
EOCH_BUFF_
STA
29
21
13
ru
0
0
–
5
0
0x031C + (X - 1) . 0x10
UDDMAX_STATUS, X in [1..6]
Read/Write
0x00000000
EOT_STA
28
20
12
ru
0
0
–
4
0
CH_BYTE_CNT
CH_BYTE_CNT
ru
ru
27
19
11
0
0
–
3
–
26
18
10
0
0
–
2
–
CH_ACTIVE
rwu
25
17
0
0
9
–
1
0
AT32UC3A
CH_EN
rwu
24
16
0
0
8
–
0
0
595