ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 59

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.5.5.3
13.5.6
13.5.6.1
13.5.6.2
32058J–AVR32–04/11
Peripheral clock masking
Clock Ready flag
Cautionary note
Mask Ready flag
caler division for the CPU clock by writing CKSEL:CPUDIV to 1 and CPUSEL to the prescaling
value, resulting in a CPU clock frequency:
Similarly, the clock for the PBA, and PBB can be divided by writing their respective bitfields. To
ensure correct operation, frequencies must be selected so that f
must never exceed the specified maximum frequency for each clock domain.
CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a
new clock setting to be written to all synchronous clocks at the same time. It is possible to keep
one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL bit-
fields. This way, it is possible to e.g. scale CPU and HSB speed according to the required
performance, while keeping the PBA and PBB frequency constant.
There is a slight delay from CKSEL is written and the new clock setting becomes effective. Dur-
ing this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER:CKRDY is written to
1, the Power Manager interrupt can be triggered when the new clock setting is effective. CKSEL
must not be re-written while CKRDY is 0, or the system may become unstable or hang.
By default, the clock for all modules are enabled, regardless of which modules are actually being
used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock
domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0.
When a module is not clocked, it will cease operation, and its registers cannot be read or written.
The module can be re-enabled later by writing the corresponding mask bit to 1.
A module may be connected to several clock domains, in which case it will have several mask
bits.
Table 13-5
Note that clocks should only be switched off if it is certain that the module will not be used.
Switching off the clock for the internal RAM will cause a problem if the stack is mapped there.
Switching off the clock to the Power Manager (PM), which contains the mask registers, or the
corresponding PBx bridge, will make it impossible to write the mask registers again. In this case,
they can only be re-enabled by a system reset.
Due to synchronization in the clock generator, there is a slight delay from a mask register is writ-
ten until the new mask setting goes into effect. When clearing mask bits, this delay can usually
be ignored. However, when setting mask bits, the registers in the corresponding module must
not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR pro-
vides the required mask status information. When writing either mask register with any value,
this bit is cleared. The bit is set when the clocks have been enabled and disabled according to
the new mask setting. Optionally, the Power Manager interrupt can be enabled by writing the
MSKRDY bit in IER.
f
CPU
= f
contains a list of implemented maskable clocks.
main
/ 2
(CPUSEL+1)
CPU
f
PBA,B
AT32UC3A
. Also, frequencies
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