ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 428

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

•
Reset value is two cycles.
In the SDRAMC, only a CAS latency of one, two and three cycles is managed.
•
Reset value is 16 bits
0: Data bus width is 32 bits.
1: Data bus width is 16 bits.
•
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
•
Reset value is seven cycles.
This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is
between 0 and 15.
•
Reset value is three cycles.
This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles
is between 0 and 15.
•
Reset value is two cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of
cycles is between 0 and 15.
•
Reset value is five cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of
cycles is between 0 and 15.
•
Reset value is height cycles.
This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is
between 0 and 15.
32058J–AVR32–04/11
CAS: CAS Latency
DBW: Data Bus Width
TWR: Write Recovery Delay
TRC: Row Cycle Delay
TRP: Row Precharge Delay
TRCD: Row to Column Delay
TRAS: Active to Precharge Delay
TXSR: Exit Self Refresh to Active Delay
0
0
1
1
CAS
0
1
0
1
CAS Latency (Cycles)
Reserved
1
2
3
AT32UC3A
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