ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 413

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.5.2
28.5.2.1
Table 28-2.
Table 28-3.
Table 28-4.
Notes:
32058J–AVR32–04/11
2
7
2
7
2
7
Bk[1:0]
2
6
2
6
2
6
Bk[1:0]
Bk[1:0]
1. M[1:0] is the byte address inside a 32-bit word.
2. Bk[1] = BA1, Bk[0] = BA0.
2
5
2
5
2
5
Software Interface
Bk[1:0]
Bk[1:0]
Bk[1:0]
32-bit Memory Data Bus Width
SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
2
4
2
4
2
4
Bk[1:0]
Bk[1:0]
Bk[1:0]
2
3
2
3
2
3
Bk[1:0]
Bk[1:0]
2
2
2
2
2
2
Bk[1:0]
The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller
allows mapping different memory types according to the values set in the SDRAMC configura-
tion register.
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user.
user in correlation with the device structure. Various configurations are illustrated.
2
1
2
1
2
1
2
0
2
0
2
0
Row[12:0]
Row[11:0]
Table 28-2
1
9
1
9
1
9
Row[10:0]
Row[12:0]
Row[11:0]
1
8
1
8
1
8
Row[10:0]
Row[12:0]
Row[11:0]
1
7
1
7
1
7
Row[10:0]
Row[12:0]
to
Row[11:0]
1
6
1
6
1
6
Table 28-7
Row[10:0]
CPU Address Line
1
5
CPU Address Line
1
5
CPU Address Line
1
5
1
4
1
4
1
4
illustrate the SDRAM device memory mapping seen by the
1
3
1
3
1
3
1
2
1
2
1
2
1
1
1
1
1
1
1
0
1
0
1
0
9
9
9
8
Column[10:0]
8
Column[10:0]
8
Column[10:0]
Column[9:0]
Column[9:0]
Column[9:0]
7
7
7
Column[8:0]
Column[8:0]
Column[8:0]
Column[7:0]
Column[7:0]
Column[7:0]
6
6
6
5
5
5
AT32UC3A
4
4
4
3
3
3
2
2
2
1
1
1
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
413
0
0
0