ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 527

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 30-27. Example of an OUT Pipe with 1 Data Bank
Figure 30-28. Example of an OUT Pipe with 2 Data Banks and no Bank Switching Delay
Figure 30-29. Example of an OUT Pipe with 2 Data Banks and a Bank Switching Delay
30.7.3.12
32058J–AVR32–04/11
TXOUTI
FIFOCON
TXOUTI
FIFOCON
TXOUTI
FIFOCON
CRC Error
SW
SW
write data to CPU
SW
This error exists only for isochronous IN pipes. It raises the CRC Error interrupt (CRCERRI),
what triggers a PXINT interrupt if CRCERRE = 1.
A CRC error can occur during IN stage if the USB controller detects a corrupted received packet.
The IN packet is stored in the bank as if no CRC error had occurred (RXINI is raised).
write data to CPU
write data to CPU
BANK 0
BANK 0
BANK 0
SW
SW
SW
OUT
OUT
OUT
SW
SW
write data to CPU
(bank 0)
write data to CPU
DATA
BANK 1
(bank 0)
DATA
(bank 0)
BANK 1
DATA
ACK
HW
SW
HW
ACK
HW
ACK
SW
OUT
SW
SW
OUT
write data to CPU
SW
write data to CPU
(bank 1)
write data to CPU
DATA
BANK0
BANK 0
BANK0
(bank 1)
DATA
ACK
AT32UC3A
SW
OUT
ACK
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