ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 263

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.7.1.1
25.7.1.2
32058J-AVR32-04/11
Clock Divider
Transmitter Clock Management
Figure 25-4. Divided Clock Block Diagram
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its
maximal value is 4095) in the Clock Mode Register CMR, allowing a Master Clock division by up
to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is
programmed to 0, the Clock Divider is not used and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Mas-
ter Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master
Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of
whether the DIV value is even or odd.
Figure 25-5.
Table 25-2.
The transmitter clock is generated from the receiver clock or the divider clock or an external
clock scanned on the TX_CLOCK I/O pad. The transmitter clock is selected by the CKS field in
TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the
CKI bits in TCMR.
Maximum
CLK_SSC / 2
Divided Clock
Master Clock
Master Clock
Divided Clock
Divided Clock Generation
DIV = 3
DIV = 1
CLK_SSC
/ 2
Divided Clock Frequency = CLK_SSC/2
Divided Clock Frequency = CLK_SSC/6
Clock Divider
12-bit Counter
Minimum
CLK_SSC / 8190
CMR
Divided Clock
AT32UC3A
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