ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 617

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.8.3.13
Offset:
Register Name:
Access Type:
Reset Value:
• RXINI: Received IN Data Interrupt Flag
Set by hardware when a new USB message is stored in the current bank of the Pipe. This triggers an interrupt if the RXINE
bit is set. Shall be cleared by software (by setting the RXINIC bit).
• TXOUTI: Transmitted OUT Data Interrupt Flag
Set by hardware when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is set.
Shall be cleared by software (by setting the TXOUTIC bit).
• TXSTPI: Transmitted SETUP Interrupt Flag
For Control endpoints. Set by hardware when the current SETUP bank is free and can be filled. This triggers an interrupt if
the TXSTPE bit is set. Shall be cleared by software (by setting the TXSTPIC bit).
• UNDERFI: Underflow Interrupt Flag
Set by hardware when a transaction underflow occurs in the current isochronous or interrupt pipe. (the pipe can’t send the
OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) will be send instead of. This
triggers an interrupt if the UNDERFLE bit is set. Shall be cleared by software (by setting the UNDERFIC bit).
• PERRI: Pipe Error Interrupt Flag
Set by hardware when an error occurs on the current bank of the Pipe. This triggers an interrupt if the PERRE bit is set.
Refers to the UPERRX register to determine the source of the error. Automatically cleared by hardware when the error
source bit is cleared.
• NAKEDI: NAKed Interrupt Flag
Set by hardware when a NAK has been received on the current bank of the Pipe. This triggers an interrupt if the NAKEDE
bit is set. Shall be cleared by software (by setting the NAKEDIC bit).
32058J–AVR32–04/11
PACKETI
SHORT
31
23
15
–
0
0
7
0
r
CURRBK
USB Pipe X Status Register (UPSTAX)
r
RXSTALLDI/
CRCERRI
30
22
14
0
0
0
6
0
r
PBYCT
r
OVERFI
29
21
13
0
0
0
5
0
r
0x0530 + X . 0x04
UPSTAX, X in [0..6]
Read-Only
0x00000000
NBUSYBK
r
NAKEDI
28
20
12
0
0
0
4
0
r
PBYCT
PERRI
27
19
11
0
–
–
3
0
r
r
UNDERFI
TXSTPI/
CFGOK
26
18
10
0
0
–
2
0
r
r
TXOUTI
25
17
0
–
9
0
1
0
r
AT32UC3A
DTSEQ
r
RWALL
RXINI
24
16
0
0
8
0
0
0
r
r
617