C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 155

DEVKIT-F120/21/22/23/24/25/26/27

C8051F120DK

Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F120DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224

Available stocks

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Manufacturer
Quantity
Price
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C8051F120DK
Manufacturer:
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Quantity:
1
11.3.2. External Interrupts
Two of the external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or
active-low edge-sensitive inputs depending on the setting of bits IT0 (TCON.0) and IT1 (TCON.2). IE0
(TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts,
respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag follows the state of the external interrupt's input pin.
The external interrupt source must hold the input active until the interrupt request is recognized. It must
then deactivate the interrupt request before execution of the ISR completes or another interrupt request
will be generated.
Interrupt Source
Reset
External Interrupt 0 (/INT0) 0x0003
Timer 0 Overflow
External Interrupt 1 (/INT1) 0x0013
Timer 1 Overflow
UART0
Timer 2
Serial Peripheral Interface 0x0033
SMBus Interface
ADC0 Window Comparator 0x0043
Programmable Counter
Array
Comparator 0 Falling Edge 0x0053
Comparator 0 Rising Edge 0x005B
Comparator 1 Falling Edge 0x0063
0x000B
0x001B
0x002B
0x003B
0x004B
0x0000
0x0023
Interru
Vector
pt
Table 11.4. Interrupt Summary
Priority
Order
Top
10
11
12
0
1
2
3
4
5
6
7
8
9
Pending Flags
None
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2 (TMR2CN.7)
EXF2 (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.3)
AD0WINT
(ADC0CN.1)
CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
N/A N/A 0
C8051F130/1/2/3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
0 EX0 (IE.0) PX0 (IP.0)
0 ET0 (IE.1) PT0 (IP.1)
0 EX1 (IE.2) PX1 (IP.2)
0 ET1 (IE.3) PT1 (IP.3)
0 ES0 (IE.4) PS0 (IP.4)
0 ET2 (IE.5) PT2 (IP.5)
0
0
0
1
2
0
1
Always
Enabled
Enable
Flag
ESPI0
(EIE1.0)
ESMB0
(EIE1.1)
EWADC0
(EIE1.2)
EPCA0
(EIE1.3)
ECP0F
(EIE1.4)
ECP0R
(EIE1.5)
ECP1F
(EIE1.6)
Priority
Control
Always
Highest
PSPI0
(EIP1.0)
PSMB0
(EIP1.1)
PWADC0
(EIP1.2)
PPCA0
(EIP1.3)
PCP0F
(EIP1.4)
PCP0R
(EIP1.5)
PCP1F
(EIP1.6)
155

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