C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 252

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
18.2. Ports 4 through 7 (100-pin TQFP devices only)
All Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O (GPIO) pins by reading and
writing the associated Port Data registers (See SFR Definition 18.13, SFR Definition 18.15, SFR Definition
18.17, and SFR Definition 18.19), a set of SFR’s which are both bit and byte-addressable. Note also that
the Port 4, 5, 6, and 7 registers are located on SFR Page F. The SFRPAGE register must be set to 0x0F to
access these Port registers.
A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regard-
less of whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs
during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC,
CLR, SETB, and the bitwise MOV write operation). During the read cycle of the read-modify-write instruc-
tion, it is the contents of the Port Data register, not the state of the Port pins themselves, which is read.
Note that at clock rates above 50 MHz, when a pin is written and then immediately read (i.e. a write instruc-
tion followed immediately by a read instruction), the propagation delay of the port drivers may cause the
read instruction to return the previous logic level of the pin.
18.2.1. Configuring Ports which are not Pinned Out
Although P4, P5, P6, and P7 are not brought out to pins on the 64-pin TQFP devices, the Port Data regis-
ters are still present and can be used by software. Because the digital input paths also remain active, it is
recommended that these pins not be left in a ‘floating’ state in order to avoid unnecessary power dissipa-
tion arising from the inputs floating to non-valid logic levels. This condition can be prevented by any of the
following:
18.2.2. Configuring the Output Modes of the Port Pins
The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull
configuration, a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to
GND, and a logic 1 will cause the Port pin to be driven to V
the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will
cause the Port pin to assume a high-impedance state. The Open-Drain configuration is useful to prevent
contention between devices in systems where the Port pin participates in a shared interconnection in
which multiple outputs are connected to the same physical wire.
252
Bits7–0: P3MDOUT.[7:0]: Port3 Output Mode Bits.
R/W
Bit7
1. Leave the weak pullup devices enabled by setting WEAKPUD (XBR2.7) to a logic 0.
2. Configure the output modes of P4, P5, P6, and P7 to “Push-Pull” by writing PnMDOUT = 0xFF.
3. Force the output states of P4, P5, P6, and P7 to logic 0 by writing zeros to the Port Data regis-
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
ters: P4 = 0x00, P5 = 0x00, P6= 0x00, and P7 = 0x00.
R/W
Bit6
SFR Definition 18.12. P3MDOUT: Port3 Output Mode
R/W
Bit5
R/W
Bit4
Rev. 1.4
R/W
Bit3
DD
. In the Open-Drain configuration, a logic 0 in
R/W
Bit2
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
0xA7
F
00000000
Reset Value