C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 250

DEVKIT-F120/21/22/23/24/25/26/27

C8051F120DK

Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F120DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F120DK
Manufacturer:
SiliconL
Quantity:
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Part Number:
C8051F120DK
Manufacturer:
*
Quantity:
1
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
250
Bits7–0: P1MDOUT.[7:0]: Port1 Output Mode Bits.
Bits7–0: P2.[7:0]: Port2 Output Latch Bits.
Note:
Note:
P2.7
R/W
R/W
Bit7
Bit7
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P2MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P2.n pin is logic low.
1: P2.n pin is logic high.
P2.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See
Memory Interface and On-Chip XRAM” on page 219
External Memory Interface.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
P2.6
R/W
R/W
Bit6
Bit6
SFR Definition 18.8. P1MDOUT: Port1 Output Mode
P2.5
R/W
R/W
Bit5
Bit5
SFR Definition 18.9. P2: Port2 Data
P2.4
R/W
R/W
Bit4
Bit4
Rev. 1.4
P2.3
R/W
R/W
Bit3
Bit3
P2.2
R/W
R/W
Bit2
Bit2
for more information about the
Section “17. External Data
P2.1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Page:
SFR Page:
P2.0
R/W
Address:
R/W
Bit0
Bit0
SFR
0xA5
F
0xA0
All Pages
Addressable
00000000
Reset Value
Reset Value
11111111
Bit

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